1. Field of the Invention
The present invention relates in general to the field of logic circuits and, more specifically, to an improved logic methodology that combines the speed advantages of dynamic logic with the low contention of static logic, such that the circuits are not adversely affected by high leakage transistors. This is accomplished through the use of a circuit comprising leakage-tolerant dynamic and static logic.
2. Description of the Related Art
As semiconductor fabrication processes continue to advance, the leakage current (i.e., the residual current through a transistor when it is supposed to be “off”) continues to increase at an exponential rate. This leakage current causes unwanted power dissipation as well as functional problems for dynamic logic.
In a dynamic logic circuit, there is a precharged node that must maintain its value near Vdd during the evaluation phase in order for the circuit to work properly. This is usually done by adding a small pMOS transistor (keeper) whose drain is connected to the precharge node, source is connected to Vdd, and gate is connected to the circuit output (i.e., the precharge node through an inverting static gate).
With the very high leakage currents of modern process technologies, the keeper must be so large for most types of dynamic circuits that the speed of the dynamic circuit is adversely affected, thus eliminating one of the primary reasons for using dynamic circuits. The speed is hindered because the dynamic logic nMOS pull-down evaluation transistors must “fight” (or “contend with”) the keeper in order to switch the gate logic value.
In view of the foregoing, there is a need for improved logic circuitry that has speed similar to dynamic logic, but with the leakage insensitivity of static logic.